p525 A Fully Integrated 1.2-GHz CMOS Phase-Locked Loop

Abstract:
A 1.2GHz phase-locked loop (PLL) is designed in a 0.18um 3.3V 1P6M CMOS RF technology.

I. Introduction
II. PLL Design

(page 2)
2.1 LC Oscillator
The circuit of LC VCO used in this paper is shown
in Fig.2.

2.2 Frequency Divider and Prescaler
In the PLL, there are two dividers, the reference
divider and the feedback divider.

Because output frequency of the VCO is very high,
a high frequency prescaler should be added between
VCO and the feedback divider [4].

(page 2)

2.3 Phase Detector and Loop Filter
Fig.5 shows the schematic of the phase/frequency
detector.

(page 3 col 2)
2.4 Charge Pump

(page 4)

III. Experimental Results